The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device.
Many modern day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory retains its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is one promising candidate for the next generation of non-volatile memory due to its simple structure and its compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
For oxide ReRAMs, electroforming of a current conducting filament is needed. This process relies on randomness and thus the position of the filament of the oxide ReRAM is not well controlled. This results in a higher forming voltage as the ReRAM cell is scaled and higher device variability.
Also, the use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of CMOS devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.
In view of the above, there is need to provide a semiconductor structure containing a resistive random access memory device integrated with a nanosheet containing device (i.e., a gate-all-around nanosheet CMOS device).